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p83c660x2, p87c660x2 p83c661x2, p87c661x2 80c51 8-bit microcontroller family 16kb otp/rom, 512b ram low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces product data supersedes data of 2003 jun 19 2003 oct 02 integrated circuits
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2 2003 oct 02 853-2416 30396 description the devices are single-chip 8-bit microcontrollers manufactured in an advanced cmos process and are derivatives of the 80c51 microcontroller family. the instruction set is 100% compatible with the 80c51 instruction set. the devices support 6-clock/12-clock mode selection by programming an otp bit (ox2) using parallel programming. in addition, an sfr bit (x2) in the clock control register (ckcon) also selects between 6-clock/12-clock mode. these devices have either one or two i 2 c interfaces, capable of handling speeds up to 400 kbits/s (fast i 2 c). they also have four 8-bit i/o ports, three 16-bit timer/event c ounters, a multi-source, four-priority-level, nested interrupt structure, an enhanced uart and on-chip oscillator and timing circuits. the added features of the p8xc66xx2 make it a powerful microcontroller for applications that require pulse width modulation, high-speed i/o, i 2 c communication, and up/down counting capabilities such as motor control. features ? 80c51 central processing unit 16 kbytes otp (87c660x2, 87c661x2) 16 kbytes rom (83c660x2, 83c661x2) 512 byte ram boolean processor fully static operation low voltage (2.7 v to 5.5 v at 16 mhz) operation ? 12-clock operation with selectable 6-clock operation (via software or via parallel programmer) ? memory addressing capability up to 64 kbytes rom and 64 kbytes ram ? power control modes: clock can be stopped and resumed idle mode power-down mode ? cmos and ttl compatible ? two speed ranges at v cc = 5 v 0 to 30 mhz with 6-clock operation 0 to 33 mhz with 12-clock operation ? parallel programming with 87c51 compatible hardware interface to programmer ? ram expandable externally to 64 kbytes ? programmable counter array (pca) pwm capture/compare ? plcc and lqfp packages ? extended temperature ranges ? dual data pointers ? security bits (3 bits) ? encryption array - 64 bytes ? 8/9 interrupt sources ? four interrupt priority levels ? four 8-bit i/o ports ? one i 2 c serial port interface has a selectable data transfer mode, either 400 kb/sec fast-mode or 100 kb/sec standard-mode (8xc660x2 and 8xc661x2) ? a second i 2 c serial port interface has the 400 kb/sec fast data-transfer mode only and selectable slew rate control of the output pins (8xc661x2) ? full-duplex enhanced uart framing error detection automatic address recognition ? three 16-bit timers/counters t0, t1 (standard 80c51) and additional t2 (capture and compare) ? programmable clock-out pin ? asynchronous port reset ? low emi (inhibit ale, slew rate controlled outputs, and 6-clock mode) ? wake-up from power down by an external interrupt
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 3 selection table type memory timers serial interfaces ram rom otp flash # of timers pwm pca wd uart i 2 c can spi adc bits/ch. i/o pins interrupts (ext.)/levels program security default clock rate optional clock rate reset active low/high? max. freq. at 6-clk / 12-clk (mhz) freq. range at 3v (mhz) (6-clk / 12-clk) freq. range at 5v (mhz) (6-clk / 12-clk) p87c660x2 512b 16k 4 1 32 7(2)/4 12-clk 6-clk h 30/33 0-16 0-30/33 p83c660x2 512b 16k 4 1 32 7(2)/4 12-clk 6-clk h 30/33 0-16 0-30/33 p87c661x2 512b 16k 4 2 32 7(2)/4 12-clk 6-clk h 30/33 0-16 0-30/33 p83c661x2 512b 16k 4 2 32 7(2)/4 12-clk 6-clk h 30/33 0-16 0-30/33 ordering information type number package temp range ( c) otp rom ram name description version ( c) P83C660X2FA 16 kb 512b plcc44 plastic leaded chip carrier; 44 leads sot1872 40 to +85 p83c660x2bbd 16 kb 512b lqfp44 plastic low profile quad flat package; 44 leads; body 10 10 1.4 mm sot3891 0 to +70 p87c660x2fa 16 kb 512b plcc44 plastic leaded chip carrier; 44 leads sot1872 40 to +85 p87c660x2bbd 16 kb 512b lqfp44 plastic low profile quad flat package; 44 leads; body 10 10 1.4 mm sot3891 0 to +70 p83c661x2fa 16 kb 512b plcc44 plastic leaded chip carrier; 44 leads sot1872 40 to +85 p83c661x2bbd 16 kb 512b lqfp44 plastic low profile quad flat package; 44 leads; body 10 10 1.4 mm sot3891 0 to +70 p87c661x2fa 16 kb 512b plcc44 plastic leaded chip carrier; 44 leads sot1872 40 to +85 p87c661x2bbd 16 kb 512b lqfp44 plastic low profile quad flat package; 44 leads; body 10 10 1.4 mm sot3891 0 to +70
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 4 block diagram 1 su01735 accelerated 80c51 cpu (12-clk mode, 6-clk mode) 8k / 16k / 32k / 64 kbyte code otp 512 / 1024 byte data ram port 3 configurable i/os port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os oscillator crystal or resonator full-duplex enhanced uart timer 0 timer 1 timer 2 programmable counter array (pca) watchdog timer fast/standard i 2 c fast i 2 c 1 1. 2nd i 2 c on p8xc661x2 only.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 5 block diagram (cpu-oriented) su01761 psen ea v pp ale rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch otp memory register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr's multiple p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 sfrs timers p.c.a. 8 8 16 serial i 2 c port sda scl serial i 2 c port sda1 scl1 serial uart port txd rxd
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 6 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 int1 cex3/t0 cex4/t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su01736 cex0 cex1 cex2 scl0 sda0 scl1 sda1 pinning plastic leaded chip carrier p8xc660x2/661x2 6140 7 17 39 29 18 28 pin function 1 nic 1 (8xc660)/ sda1 3 (8xc661) 2 p1.0/t2 3 p1.1/t2ex 4 p1.2/eci 5 p1.3/cex0 6 p1.4/cex1 7 p1.5/cex2 8 p1.6/scl0 9 p1.7/sda0 10 rst 11 p3.0/rxd 12 v ss 3 2 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0/cex3 17 p3.5/t1/cex4 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 1 23 nic 1 (8xc660)/ scl1 3 (8xc661) 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 pin function 30 p2.6/a14 31 p2.7/a15 32 psen 33 ale 34 v ss 2 2 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su01737 1. no internal connection 2. may be left open, but it is recommended to connect v ss 2 and v ss 3 to gnd to improve emc performance 3. p8xc661x2 devices only, these pins are open-drain and have the same electrical characteristics as p1.6 and p1.7 plastic quad flat pack p8xc660x2/661x2 44 34 1 11 33 23 12 22 su01738 pin function 1 p1.5/cex2 2 p1.6/scl0 3 p1.7/sda0 4 rst 5 p3.0/rxd 6v ss 3 2 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0/cex3 11 p3.5/t1/cex4 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 1 17 nic 1 (8xc660)/ scl1 3 (8xc661) 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale 28 v ss 2 2 29 ea /v pp pin function 30 p0.7/ad7 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nic 1 (8xc660)/ sda1 3 (8xc661) 40 p1.0/t2 41 p1.1/t2ex 42 p1.2/eci 43 p1.3/cex0 44 p1.4/cex1 1. no internal connection 2. may be left open, but it is recommended to connect v ss 2 and v ss 3 to gnd to improve emc performance 3. p8xc661x2 devices only
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 7 pin descriptions mnemonic pin number type name and function mnemonic plcc lqfp type name and function v ss1 22 16 i ground: 0 v reference. v ss2 34 28 i ground: additional ground pin (may be left open). v ss3 12 6 i ground: additional ground pin (may be left open). v cc 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 2 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0p1.7 2 29 4044, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). alternate functions for p8xc660x2/661x2 port 1 include: 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout (see programmable clock-out) 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 4 42 i eci (p1.2): external clock input to the pca 5 43 i/o cex0 (p1.3): capture/compare external i/o for pca module 0 6 44 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 7 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 8 2 i/o scl (p1.6): i 2 c bus clock line (open drain) 9 3 i/o scl (p1.7): i 2 c bus data line (open drain) p2.0p2.7 2 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when em itting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 2 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the p8xc660x2/661x2, as listed below: 11 5 i rxd (p3.0): serial input port 13 7 o txd (p3.1): serial output port 14 8 i int0 (p3.2): external interrupt 0 15 9 i int1 (p3.3): external interrupt 1 16 10 i cex3/t0 (p3.4): timer 0 external input; capture/compare external i/o for pca module 3 17 11 i cex4/t1 (p3.5): timer 1 external input; capture/compare external i/o for pca module 4 18 12 o wr (p3.6): external data memory write strobe 19 13 o rd (p3.7): external data memory read strobe rst 2 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal resistor to v ss permits a power-on reset using only an external capacitor to v cc . scl1 23 17 i/o second i 2 c bus clock line (open drain) (p8xc661x2) sda1 1 39 i/o second i 2 c bus data line (open drain) (p8xc661x2)
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 8 mnemonic name and function type pin number mnemonic name and function type lqfp plcc ale 2 33 27 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale can be disabled by setting sfr auxiliary.0. with this bit set, ale will be active only during a movx instruction. psen 2 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea 2 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations. if ea is held high, the device executes from internal program memory. the value on the ea pin is latched when rst is released and any subsequent changes have no effect. this pin also receives the programming supply voltage (v pp ) during programming. xtal1 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the inverting oscillator amplifier. note: 1. to avoid alatch-upo effect at power-on, the voltage on any pin (other than ea) must not be higher than v cc + 0.5 v or less than v ss 0.5 v. 2. the pins are designed for test mode also.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 9 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh srd fme extram ao xxxx0x10b auxr1# auxiliary 1 a2h lpep gps 0 dps xxxx00x0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccap0h# module 0 capture high fah xxxxxxxxb ccap1h# module 1 capture high fbh xxxxxxxxb ccap2h# module 2 capture high fch xxxxxxxxb ccap3h# module 3 capture high fdh xxxxxxxxb ccap4h# module 4 capture high feh xxxxxxxxb ccap0l# module 0 capture low eah xxxxxxxxb ccap1l# module 1 capture low ebh xxxxxxxxb ccap2l# module 2 capture low ech xxxxxxxxb ccap3l# module 3 capture low edh xxxxxxxxb ccap4l# module 4 capture low eeh xxxxxxxxb ccapm0# module 0 mode c2h ecom capp capn mat tog pwm eccf x0000000b ccapm1# module 1 mode c3h ecom capp capn mat tog pwm eccf x0000000b ccapm2# module 2 mode c4h ecom capp capn mat tog pwm eccf x0000000b ccapm3# module 3 mode c5h ecom capp capn mat tog pwm eccf x0000000b ccapm4# module 4 mode c6h ecom capp capn mat tog pwm eccf x0000000b c7 c6 c5 c4 c3 c2 c1 c0 ccon*# pca counter control c0h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b ch# pca counter high f9h 00h cl# pca counter low e9h 00h cmod# pca counter mode c1h cidl wdte cps1 cps0 ecf 00xxx000b ckcon clock control 8fh x2 xxxxxxx1b dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ec es1 es0 et1 ex1 et0 ex0 00000000b ien1* interrupt enable 1 e8h es2 et2 xxxxxx00b bf be bd bc bb ba b9 b8 ip*# interrupt priority b8h pt2 ppc ps1 ps0 pt1 px1 pt0 px0 00000000b b7 b6 b5 b4 b3 b2 b1 b0 iph# interrupt priority high b7h pt2h ppch ps1h ps0h pt1h px1h pt0h px0h 00000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1*# port 1 90h sda scl cex2 cex1 cex0 eci t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source. 2. 8xc661x2 only.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 10 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value p3* port 3 b0h rd wr t1/ cex4 t0/ cex3 int1 int0 txd rxd ffh pcon# 1 power control 87h smod1 smod0 pof gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw program status word d0h cy ac f0 rs1 rs0 ov f1 p 000000x0b rcap2h # timer 2 capture high cbh 00h rcap2l # timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 00h t2mod# timer 2 mode control c9h t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h s1con i2c control d8h cr2 ena1 sta sto si aa cr1 cr0 00h s1sta i2c status d9h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h s1dat i2c data dah 00h s1adr i2c address dbh gc 00h s2con 2 second i 2 c control f8h cr2 ena1 sta sto si aa cr1 cr0 00h s2sta 2 second i 2 c f1h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h s2dat 2 second i 2 c f2h 00h s2adr 2 second i 2 c f3h gc 00h s2ist 2 second i 2 c f4h ip1 2 interrupt priority 1 e7h ps2 00h ip1h 2 f7h ps2h 00h wdtrst watchdog timer reset a6h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source. 2. 8xc661x2 only.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 11 clock control register (ckcon) this device allows control of the 6-clock/12-clock mode by means of both an sfr bit (x2) and an otp bit. the otp clock control bit ox2, when programmed by a parallel programmer (6-clock mode), supersedes the x2 bit (ckcon.0). the ckcon register is shown below in figure 1. x2 bit symbol function ckcon.7 reserved. ckcon.6 reserved. ckcon.5 reserved. ckcon.4 reserved. ckcon.3 reserved. ckcon.2 reserved. ckcon.1 reserved. ckcon.0 x2 cpu clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle su01689 not bit addressable ckcon address = 8fh reset value = x0000000b 76543210 figure 1. clock control (ckcon) register also please note that the clock divider applies to the serial port for modes 0 & 2 (fixed baud rate modes). this is because modes 1 & 3 (variable baud rate modes) use either timer 1 or timer 2. below is the truth table for the cpu clock mode. table 1. ox2 clock mode bit (can only be set by parallel programmer) x2 bit (ckcon.0) cpu clock mode erased 0 12-clock mode (default) erased 1 6-clock mode programmed x 6-clock mode reset a reset is accomplished by holding the rst pin high for at least two machine cycles (12 osc illator periods in 6-clock mode, or 24 oscillator periods in 12-clock mode), while the oscillator is running. to ensure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above v ih1 (min.) is applied to rst. the value on the ea pin is latched when rst is deasserted and has no further effect.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 12 low power modes stop clock mode the static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power down mode is suggested. idle mode in the idle mode (see table 2), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power down mode (see table 2) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2 v and care must be taken to return v cc to the minimum specified operating voltages before the power down mode is terminated. either a hardware reset or external interrupt can be used to exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. lpep the eprom array contains some analog circuits that are not required when v cc is less than 3.6 v but are required for a v cc greater than 3.6 v. the lpep bit (auxr.4), when set, will powerdown these analog circuits resulting in a reduced supply current. this bit should be set only for applications that operate at a v cc less than 4 v. power-on flag the power-on flag (pof) is set by on-chip circuitry when the v cc level on the p8xc66xx2 rises from 0 to 5 v. the pof bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. the v cc level must remain above 3 v for the pof to remain unaffected by the v cc level. design consideration when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once ? mode the once (aon-circuit emulationo) mode facilitates testing and debugging of systems without the device having to be removed from the circuit. the once mode is invoked by: 1. pull ale low while the device is in reset and psen is high; 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the device is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 61 hz to 4 mhz at a 16 mhz operating frequency in 12-clock mode (122 hz to 8 mhz in 6-clock mode). to configure the timer/counter 2 as a clock generator, bit c/t 2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n (65536 rcap2h, rcap2l) n = 2 in 6-clock mode 4 in 12-clock mode where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency will be the same.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 13 table 2. external pin status during idle and power-down mode mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data timer 0 and timer 1 operation timer 0 and timer 1 the atimero or acountero function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 3 shows the mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfn. the counted input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements). trn is a control bit in the special function register tcon (figure 4). the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). mode 1 mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 5. overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which is preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 as for timer 1. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 6. tl0 uses the timer 0 control bits: c/t , gate, tr0, and tf0 as well as pin int0 . th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an 80c51 can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 14 gate c/t m1 m0 gate c/t m1 m0 bit symbol function tmod.3/ gate gating control when set. timer/counter ano is enabled only while aintn o pin is high and tmod.7 atrno control pin is set. when cleared timer ano is enabled whenever atrno control bit is set. tmod.2/ c/t timer or counter selector cleared for timer operation (input from internal system clock.) tmod.6 set for counter operation (input from atno input pin). m1 m0 operating 0 0 8048 timer: atlno serves as 5-bit prescaler. 0 1 16-bit timer/counter: athno and atlno are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter: athno holds a value which is to be reloaded into atlno each time it overflows. 1 1 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 (timer 1) timer/counter 1 stopped. su01580 timer 1 timer 0 not bit addressable tmod address = 89h reset value = 00h 76543 2 1 0 figure 2. timer/counter 0/1 mode control (tmod) register intn pin timer n gate bit trn tln (5 bits) thn (8 bits) tfn interrupt control c/t = 0 c/t = 1 su01618 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 3. timer/counter 0/1 mode 0: 13-bit timer/counter
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 15 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. su01516 ie0 it1 ie1 tr0 tf0 tr1 tf1 bit addressable tcon address = 88h reset value = 00h 76543210 figure 4. timer/counter 0/1 control (tcon) register tln (8 bits) tfn interrupt control c/t = 0 c/t = 1 thn (8 bits) reload intn pin timer n gate bit trn su01619 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 5. timer/counter 0/1 mode 2: 8-bit auto-reload
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 16 tl0 (8 bits) tf0 interrupt control th0 (8 bits) tf1 interrupt control tr1 int0 pin timer 0 gate bit tr0 su01620 c/t = 0 c/t = 1 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. osc d* osc d* t0 pin figure 6. timer/counter 0 mode 3: two 8-bit counters
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 17 timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t 2 in the special function register t2con (see figure 1). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator, which are selected by bits in the t2con as shown in table 3. capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t 2 in t2con) which, upon overflowing sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2= 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt). the capture mode is illustrated in figure 2 (there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/6 pulses (osc/12 in 12-clock mode).). auto-reload mode (up or down counter) in the 16-bit auto-reload mode, timer 2 can be configured (as either a timer or counter [c/t 2 in t2con]) then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see figure 3). when reset is applied the dcen=0 which means timer 2 will default to counting up. if dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 4 shows timer 2 which will count up automatically since dcen=0. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software means. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. in figure 5 dcen=1 which enables timer 2 to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt, if the interrupt is enabled. this timer overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation. (msb) (lsb) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t 2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/6 in 6-clock mode or osc/12 in 12-clock mode) 1 = external event counter (falling edge triggered). cp/rl 2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 su01251 figure 1. timer/counter 2 (t2con) control register
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 18 table 3. timer 2 operating modes rclk + tclk cp/rl 2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off) osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture su01252 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 2. timer 2 in capture mode not bit addressable symbol function e not implemented, reserved for future use.* t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. e e e e e e t2oe dcen su00729 76543210 * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reser ved bit is indeterminate. bit t2mod address = 0c9h reset value = xxxx xx00b figure 3. timer 2 mode (t2mod) control register
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 19 osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload su01253 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 4. timer 2 in auto-reload mode (dcen = 0) n* c/t 2 = 0 c/t 2 = 1 tl2 th2 tr2 control t2 pin su01254 ffh ffh rcap2l rcap2h (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle osc * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 5. timer 2 auto reload mode (dcen = 1)
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 20 c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector reload 2 a0o a1o rx clock 16 tx clock a0o a1o a0o a1o timer 1 overflow note availability of additional external interrupt. smod rclk tclk su01629 n = 1 in 6-clock mode n = 2 in 12-clock mode osc n t2 pin figure 6. timer 2 in baud rate generator mode table 4. timer 2 generated commonly used baud rates baud rate timer 2 12-clock mode 6-clock mode osc freq rcap2h rcap2l 375 k 750 k 12 mhz ff ff 9.6 k 19.2 k 12 mhz ff d9 4.8 k 9.6 k 12 mhz ff b2 2.4 k 4.8 k 12 mhz ff 64 1.2 k 2.4 k 12 mhz fe c8 300 600 12 mhz fb 1e 110 220 12 mhz f2 af 300 600 6 mhz fd 8f 110 220 6 mhz f9 57 baud rate generator mode bits tclk and/or rclk in t2con (table 4) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk= 0, timer 1 is used as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates one generated by timer 1, the other by timer 2. figure 6 shows the timer 2 in baud rate generation mode. the baud rate generation mode is like the auto-reload mode,in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below: modes 1 and 3 baud rates timer 2 overflow rate 16 the timer can be configured for either atimero or acountero operation. in many applications, it is configured for atimero operation (c/t 2=0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1 / 6 the oscillator frequency in 6-clock mode, 1 / 12 the oscillator frequency in 12-clock mode). as a baud rate generator, it increments at the oscillator frequency in 6-clock mode ( osc / 2 in 12-clock mode). thus the baud rate formula is as follows: oscillator frequency [n* [65536 (rcap2h, rcap2l)]] modes 1 and 3 baud rates = * n = 16 in 6-clock mode 32 in 12-clock mode where: (rcap2h, rcap2l)= the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure 6, is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 21 when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented every state time (osc/2) or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. table 4 shows commonly used baud rates and how they can be obtained from timer 2. summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2 (p1.0) the baud rate is: baud rate timer 2 overflow rate 16 if timer 2 is being clocked internally, the baud rate is: baud rate f osc [n* [65536 (rcap2h, rcap2l)]] * n = 16 in 6-clock mode 32 in 12-clock mode where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l 65536 f osc n* baud rate timer/counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 5 for set-up of timer 2 as a timer. also see table 6 for set-up of timer 2 as a counter. table 5. timer 2 as a timer t2con mode internal control (note 1) external control (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 6. timer 2 as a counter tmod mode internal control (note 1) external control (note 2) 16-bit 02h 0ah auto-reload 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generator mode.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 22 full-duplex enhanced uart standard uart operation the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 7. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12 (12-clock mode) or / 6 (6-clock mode). the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. in 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. mode 2 baud rate = 2 smod n (oscillator frequency) where: n = 64 in 12-clock mode, 32 in 6-clock mode the baud rates in modes 1 and 3 are determined by the timer 1 or timer 2 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator (t2con.rclk = 0, t2con.tclk = 0), the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate = 2 smod n (timer 1 overflow rate) where: n = 32 in 12-clock mode, 16 in 6-clock mode the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate = 2 smod n oscillator frequency 12 [256(th1)] where: n = 32 in 12-clock mode, 16 in 6-clock mode one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 8 lists various commonly used baud rates and how they can be obtained from timer 1.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 23 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was no t received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the o ther modes, in any serial transmission. must be cleared by software. ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the o ther modes, in any serial reception (except see sm2). must be cleared by software. sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 (12-clock mode) or f osc /6 (6-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 (12-clock mode) or f osc /32 or f osc /16 (6-clock mode) 1 1 3 9-bit uart variable su01626 bit addressable scon address = 98h reset value = 00h 76543 210 figure 7. serial port control (scon) register baud rate f smod timer 1 mode 12-clock mode 6-clock mode f osc smod c/t mode reload value mode 0 max 1.67 mhz 3.34 mhz 20 mhz x x x x mode 2 max 625 k 1250 k 20 mhz 1 x x x mode 1, 3 max 104.2 k 208.4 k 20 mhz 1 0 2 ffh mode 1, 3 19.2 k 38.4 k 11.059 mhz 1 0 2 fdh 9.6 k 19.2 k 11.059 mhz 0 0 2 fdh 4.8 k 9.6 k 11.059 mhz 0 0 2 fah 2.4 k 4.8 k 11.059 mhz 0 0 2 f4h 1.2 k 2.4 k 11.059 mhz 0 0 2 e8h 137.5 275 11.986 mhz 0 0 2 1dh 110 220 6 mhz 0 0 2 72h 110 220 12 mhz 0 0 1 feebh figure 8. timer 1 generated commonly used baud rates more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). figure 9 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 24 shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the 80c51 the baud rate is determined by the timer 1 or timer 2 overflow rate. figure 10 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9the data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1 or timer 2. figures 11 and 12 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after awrite to subf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 25 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send shift start s6 rx control start shift receive rx clock t1 r1 serial port interrupt 1 1 1 1 1 1 1 0 input shift register ren ri load sbuf shift shift clock rxd p3.0 alt output function txd p3.1 alt output function sbuf read sbuf 80c51 internal bus rxd p3.0 alt input function write to sbuf s6p2 send shift rxd (data out) d0 d1 d2 d3 d4 d5 d6 d7 transmit txd (shift clock) ti s3p1 s6p1 write to scon (clear ri) ri receive shift rxd (data in) d0 d1 d2 d3 d4 d5 d6 txd (shift clock) s5p2 receive d7 ale s4 . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 su00539 lsb lsb msb msb figure 9. serial port mode 0
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 26 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock ri t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rxd rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data 16 load sbuf shift 1ffh su00540 figure 10. serial port mode 1
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 27 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start load sbuf rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 smod = 1 smod = 0 shift bit detector rxd stop bit gen. mode 2 phase 2 clock (1/2 f osc ) r1 16 shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data (smod is pcon.7) tb8 rb8 stop bit gen. su00541 figure 11. serial port mode 2
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 28 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector rxd r1 16 load sbuf shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data tb8 rb8 stop bit gen. su00542 figure 12. serial port mode 3
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 29 enhanced features the uart operates in all of the usual modes that are described in the first section of data handbook ic20, 80c51-based 8-bit microcontrollers . in addition the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 7). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 13. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 14. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to b used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 30 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su00044 figure 13. uart framing error detection sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 14. uart multiprocessor communication, automatic address recognition
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 31 sio1 and sio2, i 2 c serial i/o the i 2 c-bus is a simple bi-directional 2-wire bus to transfer information between devices connected to the bus. the main features of the bus are: ? only two bus lines are required: a serial clock line (scl) and a serial data line (sda). ? bi-directional data transfer between masters and slaves. ? each device connected to the bus is software addressable by a unique address. ? masters can operate as master-transmitter or as master-receiver. ? it is a true multi-master bus (no central master) and includes collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. ? serial clock synchronization allows devices with different bit rates to communicate via the same serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? devices can be added to or removed from an i 2 c-bus system without affecting any other device on the bus. ? fault diagnostics and debugging are simple; malfunctions can be immediately traced. for more information see the philips publication athe i 2 c-bus specificationo, especially for detailed descriptions of the fast and the standard data-transfer modes. also, refer to the data sheets for the 8xc552, the 8xc554, the 8xc557, and the 8xc65x. the sio1 i 2 c serial port interface has a selectable bi-directional data-transfer mode, either the 400kbit/s fast-mode or the 100kbit/s standard-mode. in the fast-mode, the port performance and the register definitions are identical to those of the 8xc557 devices, and in the standard-mode (the reset default), they are identical to those of the 8xc652, 8xc654, 8xc552, and 8xc554 devices. the fast-mode is functionally the same as the standard-mode except for the bit rate selection (see tables 7 and 8), the timing of the scl and sda signals (see the i 2 c electrical characteristics), and the output slew-rate control. the fast-mode allows up to a four-fold bit-rate increase over that of the standard-mode, and yet, it is downward compatible with the standard-mode, i.e. it can be used in a 0 to 100kbit/s bus system. the scl serial port for the clock line of the i 2 c bus is an alternate function of the p1.6 port pin, and the sda serial port for the data line of the i 2 c bus is an alternate function of the p1.7 port pin. consequently, these 2 port pins are open drain outputs (no pull-ups), and the output latches of p1.6 and p1.7 must be set to logic 1 in order to enable the sio1 outputs. the second i 2 c serial port of the 8xc661x2, sio2, has the 400kbit/s fast data-transfer mode only and selectable slew-rate control of the output pins. it also has the same port performance and register definitions as those of the 8xc557. the scl1 and sda1 serial ports have dedicated pins with open-drain outputs and schmitt-trigger inputs. there is an analog circuit for controlling the turn-on and turn-off rates of the output pull-down (slew-rate control circuit) which is required to meet the electrical specifications of the fast-mode under nominal conditions (5 v). to achieve the maximum slew-rates, the circuit must be disabled. for the sio1 serial port, the slew-rate control circuits for both the scl and sda pins are disabled in the standard mode (maximum slew-rate), and they are enabled in the fast-mode. for the sio2 serial port, the slew-rate control circuits for both pins are enabled by reset, but the slew-rate disable bit (srd bit) in the auxr register disables the slew-rate circuits for both the scl1 and sda1 pins when set for maximum slew-rates. this feature of the sio2 slew-rate control is very useful for higher bus loads, higher temperatures and lower voltages that cause additional decreases in slew-rates. all of the functional descriptions discussed below apply to both the sio1 and the sio2 i 2 c serial ports although the text may refer to the sio1 only. see page 10 for the corresponding sio2 register addresses. the i 2 c on-chip logic performs a byte oriented data transfer, clock generation, address recognition and bus control arbitration, and interfaces to the external i 2 c-bus via the two port pins scl and sda. it meets the i 2 c-bus specification and supports all transfer modes (other than the low-speed mode) from-and-to the i 2 c-bus. the logic handles byte transfers autonomously. it also keeps track of serial transfers, and a status register (sxsta) reflects the status of the siox logic and the i 2 c-bus. the cpu interfaces to the logic of each of the two i 2 cs via the following four special function registers (where x=1,2): ? sxcon: control register, bit addressable by the cpu. ? sxsta: status register whose contents may be used as a vector to service routines. ? sxdat: data shift register; the data byte is stable as long as the si bit = 1 (sxcon.3). ? sxadr: slave address register; its lsb enables / disables general call address recognition. a typical i 2 c-bus configuration is shown in figure 15, and figure 16 shows how a data transfer is accomplished on the bus. depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c-bus: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a anot acknowledgeo is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. modes of operation: the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode: serial data output through p1.7/sda while p1.6/scl outputs the serial clock. the first byte transmitted contains the slave address
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 32 of the receiving device (7 bytes) and the data direction bit. in this case the data direction bit (r/w ) will be logic 0, and we say that a awo is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode: the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case, the data direction bit (r/w ) will be logic 1, and we say that an aro is transmitted. thus the first byte transmitted is sla+r. serial data is received via p1.7/sda while p1.6/scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received through p1.7/sda and p1.6/scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via p1.7/sda while the serial clock is input through p1.6/scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. v dd other device with i 2 c interface p8xc66xx2 other device with i 2 c interface p1.7/sda p1.6/scl sda scl i 2 c bus r p r p su01748 figure 15. typical i 2 c bus configuration scl start condition s sda p/s msb acknowledgment signal from receiver clock line held low while interrupts are serviced 1 2 7 8 9 1 2 38 ack 9 ack repeated if more bytes are transferred acknowledgment signal from receiver slave address r/w direction bit stop condition repeated start condition su00965 figure 16. data transfer on the i 2 c bus
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 33 sio1 implementation and operation: figure 17 shows how the on-chip i 2 c bus interface is implemented, and the following text describes the individual blocks. i nput f ilters and o utput s tages the input filters have i 2 c compatible input levels. if the input voltage is less than 1.5 v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 v, the input logic level is interpreted as 1. input signals are synchronized with the internal clock (f osc /4), and spikes shorter than three oscillator periods are filtered out. the output stages consist of open drain transistors that can sink 3 ma at v out < 0.4 v. these open drain outputs do not have clamping diodes to v dd . thus, if the device is connected to the i 2 c bus and v dd is switched off, the i 2 c bus is not affected. a ddress r egister, s 1 adr this 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call address (00h) recognition. c omparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in s1adr). it also compares the first received 8-bit byte with the general call address (00h). if an equality is found, the appropriate status bits are set and an interrupt is requested. s hift r egister, s 1 dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 34 f osc /4 internal bus address register comparator shift register control register status register arbitration & sync logic timing & control logic serial clock generator ack status decoder timer 1 overflow interrupt 8 8 8 8 s1sta status bits s1con s1dat input filter output stage p1.7 input filter output stage p1.6 p1.6/scl p1.7/sda s1adr su00966 figure 17. i 2 c bus serial interface block diagram
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 35 a rbitration and s ynchronization l ogic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a anot acknowledge: (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. figure 18 shows the arbitration procedure. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the amarko duration is determined by the device that generates the shortest amarks,o and the aspaceo duration is determined by the device that generates the longest aspaces.o figure 19 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. ack 1. another device transmits identical serial data. sda 1 234 89 scl (1) (1) (2) (3) 2. another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lost, and sio1 enters the slave receiver mode. 3. sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. su00967 figure 18. arbitration procedure (1) scl (3) (1) sda mark duration space duration (2) 1. another service pulls the scl line low before the sio1 amarko duration is complete. the serial clock generator is immediately reset and commences with the aspaceo duration by pulling scl low. 2. another device still pulls the scl line low after sio1 releases scl. the serial clock generator is forced into the wait state until the scl line is released. 3. the scl line is released, and the serial clock generator commences with the mark duration. su00968 figure 19. serial clock synchronization
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 36 s erial c lock g enerator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. in standard speed mode, the programmable output clock frequencies are: f osc /120, f osc /9600, and the timer 1 overflow rate divided by eight. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. t iming and c ontrol the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the i 2 c bus status. c ontrol r egister, s 1 con this 7-bit special function register is used by the microcontroller to control the following sio1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. s tatus d ecoder and s tatus r egister the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code is sufficient for most of the service routines (see the software example in this section). the four sio1 special function registers: the microcontroller interfaces to sio1 via four special function registers. these four sfrs (s1adr, s1dat, s1con, and s1sta) are described individually in the following sections. the address register, s1adr: the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontroller's own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. s1adr (dbh) xgc 7 65 432 10 own slave address x xx xx x the most significant bit corresponds to the first bit received from the i 2 c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. the data register, s1dat: s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. s1dat (dah) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 7 65 43 2 1 0 shift direction sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. figure 20 shows how data in s1dat is serially transferred to and from the sda line. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer (bsd7) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, bsd7 is loaded with the content of s1dat.7, which is the first bit to be transmitted to the sda line (see figure 21). after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat. the control register, s1con: the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ens1 = a0o. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 cr2 ens 1, the sio 1 e nable b it ens1 = a0o: when ens1 is a0o, the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the anot addressedo slave state, and the sto bit in s1con is forced to a0o. no other bits are affected. p1.6 and p1.7 may be used as open drain i/o ports. ens1 = a1o: when ens1 is a1o, sio1 is enabled. the p1.6 and p1.7 port latches must be set to logic 1. ens1 should not be used to temporarily release sio1 from the i2c bus since, when ens1 is reset, the i2c bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text).
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 37 internal bus 8 bsd7 s1dat ack scl sda shift pulses su00969 figure 20. serial input/output configuration shift in sda scl d7 d6 d5 d4 d3 d2 d1 d0 a shift ack & s1dat ack (2) (2) (2) (2) (2) (2) (2) (2) a (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) s1dat shift bsd7 bsd7 d7 d6 d5 d4 d3 d2 d1 d0 (3) loaded by the cpu (1) valid data in s1dat (2) shifting data in s1dat and ack (3) high level on sda shift out su00970 figure 21. shift-in and shift-out timing in the following text, it is assumed that ens1 = a1o. sta , the start f lag sta = a1o: when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i2c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition (which will free the bus) and generates a start condition after a delay of a half clock period of the internal serial clock generator. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 transmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = a0o: when the sta bit is reset, no start condition or repeated start condition will be generated. sto , the stop f lag sto = a1o: when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the defined anot addressedo slave receiver mode. the sto flag is automatically cleared by hardware.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 38 if the sta and sto bits are both set, the a stop condition is transmitted to the i 2 c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = a0o: when the sto bit is reset, no stop condition will be generated. si , the s erial i nterrupt f lag si = a1o: when the si flag is set, then, if the ea and es1 (interrupt enable register) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = a0o: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. aa , the a ssert a cknowledge f lag aa = a1o: if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: the aown slave addresso has been received the general call address has been received while the general call bit (gc) in s1adr is set a data byte has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode aa = a0o: if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: a data has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 25). when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. cr 0, cr 1, and cr 2, the c lock r ate b its these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 7. for the sio1 serial port, the standard data transfer mode is the default mode after reset. to change the data transfer mode to the fastmode, the fast mode enable bit (fme bit) of the auxr register (auxr.3 bit) must be set. after setting the fme bit you cannot clear it (a onetime set bit), and it can only be cleared with a reset . for the sio2 serial port, the analog circuits for controlling the slewrates of the output pull-downs may be disabled with the slewrate disable bit (auxr.5 bit). for maximum slew rates, setting this bit disables the slewrate control circuits of the scl1 and sda1 pins. this bit is cleared by reset (reset default), and it can be set/cleared by software. this feature of the sio2 slewrate control is very useful for higher bus loads, higher temperatures and lower voltages that cause additional decreases in slewrates. auxr (8eh) a0 7 65 432 10 srd fme ex- tram a 12.5khz bit rate may be used by devices that interface to the i 2 c bus via standard i/o port lines which are software driven and slow. 100khz is usually the maximum bit rate and can be derived from a 16 mhz, 12 mhz, or a 6 mhz oscillator. a variable bit rate (0.5khz to 62.5khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in table 7 are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100khz. the status register, s1sta: s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = a1o). a valid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 39 table 7. 400 kbytes i 2 c interface serial clock rates bit frequency (khz) at f osc in 6x mode f osc divide by cr2 cr1 cr0 3 mhz 6 mhz 12 mhz 16 mhz 24 mhz 30 mhz 1 0 0 25 50 100 133 200 250 120 1 0 1 2 4 8 10 15 19 1600 1 1 0 38 75 150 200 300 375 80 1 1 1 50 100 200 267 400 500 60 0 0 0 100 200 400 533 800 1000 30 0 0 1 4 8 15 20 30 38 800 0 1 0 150 300 600 800 1200 1500 20 0 1 1 200 400 800 1067 1600 2000 15 bit frequency (khz) at f osc in 12x mode f osc divide by cr2 cr1 cr0 3 mhz 6 mhz 12 mhz 16 mhz 24 mhz 33 mhz 1 0 0 13 25 50 67 100 138 240 1 0 1 1 2 4 5 8 10 3200 1 1 0 19 38 75 100 150 206 160 1 1 1 25 50 100 133 200 275 120 0 0 0 50 100 200 267 400 550 60 0 0 1 2 4 8 10 15 21 1600 0 1 0 75 150 300 400 600 825 40 0 1 1 100 200 400 533 800 1100 30
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 40 table 8. 100 kbytes i 2 c interface serial clock rates bit frequency (khz) at f osc in 6x mode f osc divide by cr2 cr1 cr0 3 mhz 6 mhz 12 mhz 16 mhz 24 mhz 30 mhz 0 0 0 23 47 94 125 188 234 128 0 0 1 27 54 107 143 214 268 112 0 1 0 31 63 125 167 250 313 96 0 1 1 38 75 150 200 300 375 80 1 0 0 6 13 25 33 50 63 480 1 0 1 50 100 200 267 400 500 60 1 1 0 100 200 400 533 800 1000 30 1 1 1 0.2 to 31.2 0.5 to 62.5 1.0 to 125 1.3 to 167 2.0 to 250 2.4 to 313 48x(256(reload value timer1)) mode 2 value range: 0 to 254 bit frequency (khz) at f osc in 12x mode f osc divide by cr2 cr1 cr0 3 mhz 6 mhz 12 mhz 16 mhz 24 mhz 33 mhz 0 0 0 12 23 47 63 94 129 256 0 0 1 13 27 54 71 107 147 224 0 1 0 16 31 63 83 125 172 192 0 1 1 19 38 75 100 150 206 160 1 0 0 3 6 13 17 25 34 960 1 0 1 25 50 100 133 200 275 120 1 1 0 50 100 200 267 400 550 60 1 1 1 0.1 to 15.6 0.2 to 31.3 0.5 to 62.5 0.7 to 83.3 1.0 to 125 1.3 to 172 96x(256(reload val- ue timer1)) mode 2 value range: 0 to 254
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 41 more information on sio1 operating modes: the four operating modes are: master transmitter master receiver slave receiver slave transmitter data transfers in each mode of operation are shown in figures 2225. these figures contain the following abbreviations: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 22-25, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the s1sta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables 9-13. master transmitter mode: in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 22). before the master transmitter mode can be entered, s1con must be initialized as follows: s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 7 6543210 1000x bit rate bit rate cr0, cr1, and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i 2 c bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla+w). the si bit in s1con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 9. after a repeated start condition (state 10h). sio1 may switch to the master receiver mode by loading s1dat with sla+r). master receiver mode: in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 23). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 10. ens1, cr1, and cr0 are not affected by the serial transfer and are not referred to in table 10. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla+w. slave receiver mode: in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 24). to initiate the slave receiver mode, s1adr and s1con must be loaded as follows: s1adr (dbh) xgc 7 65 432 1 0 own slave address x xx xx x the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb (gc) is set, sio1 will respond to the general call address (00h); otherwise it ignores the general call address. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 x1 0001x x cr2 cr0, cr1, and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowledge its own slave address or the general call address. sta, sto, and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a0o (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 11. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 42 ???????? ???????? ??? ??? ??? ??? ??? ??? s sla wa a data p ??????? ??????? ??????? s sla w ??? ??? a p ??? ??? ??? a p 08h 18h 28h ??? ??? r 38h a or a other mst continues a or a other mst continues 38h 30h 20h 68h 78h 80h other mst continues a mt 10h to mst/rec mode entry = mr to corresponding states in slave mode successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 9. data su00971 figure 22. format and states in the master transmitter mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 43 ???????? ???????? ??? ??? s sla ra data p ??????? ??????? ??????? s sla r ??? ??? a p 08h 40h 50h ??? ??? w 38h a or a other mst continues other mst continues 38h 48h 68h 78h 80h other mst continues a mr 10h to mst/trx mode entry = mt to corresponding states in slave mode successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave ???? ???? ???? ???? ???? n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 10. ??? ??? a ???? ???? data ??? ??? a 58h ??? ??? ??? a ?? ?? data a su00972 figure 23. format and states in the master receiver mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 44 ??????? ??????? ??? ??? ???? ???? ??? ??? s sla wa a data p or s a 60h 80h 68h reception of the own slave address and one or more data bytes all are acknowledged. last data byte received is not acknowledged arbitration lost as mst and addressed as slave reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 11. data a sla ??? ??? data 80h a0h ??? ??? ??? a 88h p or s ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? general call aa data p or s 70h 90h 78h a data 90h a0h a 98h p or s a su00973 figure 24. format and states in the slave receiver mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 45 ???????? ???????? ???????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? s sla ra data p or s b0h a8h b8h reception of the own slave address and transmission of one or more data bytes a data a c0h ???? ???? ?? ?? n any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 12. data a ??? ??? ??? all a1os ??? ??? ??? a a ???? ???? from master to slave from slave to master c8h p or s last data byte transmitted. switched to not addressed slave (aa bit in s1con = a0o arbitration lost as mst and addressed as slave su00974 figure 25. format and states of the slave transmitter mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 46 table 9. master transmitter mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start diti h b load sla+w or x 0 0 x as above condition has been transmitted load sla+r x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmitted; ack has bid load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmitted; not ack hb id load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in s1dat has been transmitted; ack hb id load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in s1dat has been transmitted; not ack h b i d load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received ack has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r/w or db no s1dat action or 0 0 0 x i 2 c bus will be released; not addressed slave will be entered data bytes no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 47 table 10. master receiver mode status status of the i 2 c application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start diti h b load sla+r or x 0 0 x as above condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or 0 0 0 x i 2 c bus will be released; sio1 will enter a slave mode no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has bid no s1dat action or 0 0 0 0 data byte will be received; not ack bit will be returned been received no s1dat action 0 0 0 1 data byte will be received; ack bit will be returned 48h sla+r has been t itt d not ack no s1dat action or 1 0 0 x repeated start condition will be transmitted transmitted; not ack has been received no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been d read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned returned read data byte 0 0 0 1 data byte will be received; ack bit will be returned 58h data byte has been i d not ack h read data byte or 1 0 0 x repeated start condition will be transmitted received; not ack has been returned read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 48 table 11. slave receiver mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 60h own sla+w has been received; ack hb d no s1dat action or x 0 0 0 data byte will be received and not ack will be returned has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has b i d ack no s1dat action or x 0 0 0 data byte will be received and not ack will be returned been received, ack returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 70h general call address (00h) has been received ; ack has no s1dat action or x 0 0 0 data byte will be received and not ack will be returned received ack has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received no s1dat action or x 0 0 0 data byte will be received and not ack will be returned has been received , ack has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 80h previously addressed with own slv address; data has b i d ack read data byte or x 0 0 0 data byte will be received and not ack will be returned been received; ack has been returned read data byte x 0 0 1 data byte will be received and ack will be returned 88h previously addressed with own sla; data bhb read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address byte has been received; not ack has been returned read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data byte has been i d ack h read data byte or x 0 0 0 data byte will be received and not ack will be returned received; ack has been returned read data byte x 0 0 1 data byte will be received and ack will be returned 98h previously addressed with general call; data b h b read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address data byte has been received; not ack has been returned read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 49 table 11. slave receiver mode (continued) status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa a0h a stop condition or repeated start di i h b no stdat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address condition has been received while still addressed as slv/rec or slv/trx no stdat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 slv/rec or slv/trx no stdat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no stdat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. table 12. slave transmitter mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa a8h own sla+r has been received; ack hb d load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received has been returned load data byte x 0 0 1 data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received been received, ack has been returned load data byte x 0 0 1 data byte will be transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received ack has been received load data byte x 0 0 1 data byte will be transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack h b no s1dat action or 0 0 0 01 switched to not addressed slv mode; no recognition of own sla or general call address not ack has been received no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been i d (aa 0) no s1dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address transmitted (aa = 0); ack has been received no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 50 table 13. miscellaneous states status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa f8h no relevant state information available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an undefined state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not addressed slv mode. sto is reset. slave transmitter mode: in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 25). data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a1o (r) for sio1 to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 12. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus. miscellaneous states: there are two s1sta codes that do not correspond to a defined sio1 hardware state (see table 13). these are discussed below. s1sta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h: this status code indicates that a bus error has occurred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio1 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the anot addressedo slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is not transmitted). some special cases: the sio1 hardware has facilities to handle the following special cases that may occur during a serial transfer: simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 26). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i 2 c bus before generating a repeated start condition itself, it will release the bus, and no interrupt request is generated. if another master frees the bus by generating a stop condition, sio1 will transmit a normal start condition (state 08h), and a retry of the total serial data transfer can commence. d ata t ransfer a fter l oss of a rbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 18). loss of arbitration is indicated by the following states in s1sta; 38h, 68h, 78h, and b0h (see figures 22 and 23). if the sta flag in s1con is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. f orced a ccess to the i 2 c b us in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware (see figure 27).
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 51 s 08h sla w a data a s both masters continue with sla transmission 18h 28h other master sends repeated start condition earlier su00975 figure 26. simultaneous repeated start conditions from 2 masters sta flag time out sda line scl line start condition su00976 figure 27. forced access to a busy i 2 c bus i 2 c b us o bstructed by a l ow l evel on scl or sda an i 2 c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line (see figure 28). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i 2 c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. b us e rror a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 13.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 52 sta flag start condition (1) unsuccessful attempt to send a start condition (2) sda line released (3) successful attempt to send a start condition; state 08h is entered sda line scl line (1) (1) (2) (3) su00977 figure 28. recovering from a bus obstruction caused by a low level on sda software examples of sio1 service routines: this section consists of a software example for: initialization of sio1 after a reset entering the sio1 interrupt routine the 26 state service routines for the master transmitter mode master receiver mode slave receiver mode slave transmitter mode i nitialization in the initialization routine, sio1 is enabled for both master and slave modes. for each mode, a number of bytes of internal data ram are allocated to the sio to act as either a transmission or reception buffer. in this example, 8 bytes of internal data ram are reserved for different purposes. the data memory map is shown in figure 29. the initialization routine performs the following functions: s1adr is loaded with the part's own slave address and the general call bit (gc) p1.6 and p1.7 bit latches are loaded with logic 1s ram location hadd is loaded with the high-order address byte of the service routines the sio1 interrupt enable and interrupt priority bits are set the slave mode is enabled by simultaneously setting the ens1 and aa bits in s1con and the serial clock frequency (for master modes) is defined by loading cr0 and cr1 in s1con. the master routines must be started in the main program. the sio1 hardware now begins checking the i 2 c bus for its own slave address and general call. if the general call or the own slave address is detected, an interrupt is requested and s1sta is loaded with the appropriate state information. the following text describes a fast method of branching to the appropriate service routine. sio 1 i nterrupt r outine when the sio1 interrupt is entered, the psw is first pushed on the stack. then s1sta and hadd (loaded with the high-order address byte of the 26 service routines by the initialization routine) are pushed on to the stack. s1sta contains a status code which is the lower byte of one of the 26 service routines. the next instruction is ret, which is the return from subroutine instruction. when this instruction is executed, the high and low order address bytes are popped from stack and loaded into the program counter. the next instruction to be executed is the first instruction of the state service routine. seven bytes of program code (which execute in eight machine cycles) are required to branch to one of the 26 state service routines. si push psw save psw push s1sta push status code (low order address byte) push hadd push high order address byte ret jump to state service routine the state service routines are located in a 256-byte page of program memory. the location of this page is defined in the initialization routine. the page can be located anywhere in program memory by loading data ram register hadd with the page number. page 01 is chosen in this example, and the service routines are located between addresses 0100h and 01ffh. t he s tate s ervice r outines the state service routines are located 8 bytes from each other. eight bytes of code are sufficient for most of the service routines. a few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code. each state routine is part of the sio1 interrupt routine and handles one of the 26 states. it ends with a reti instruction which causes a return to the main program.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 53 db s1adr gc s1dat 0 0 cr0 cr! si 0 aa st0 sta cr2 ens1 special function registers 53 backup numbytmst internal data ram s1sta s1con psw da d9 d8 d0 ps1 ipo b8 ien0 ab es1 ea p1.7 p1.6 p1 90 80 7f original value of numbytmst number of bytes as master 52 sla sla+r/w to be transmitted to sla 51 hadd higher address byte interrupt routine 50 slave transmitter data ram 4f std 48 slave receiver data ram srd 40 master receiver data ram mrd 38 master transmitter data ram mtd 30 19 r1 r0 18 00 su00978 figure 29. sio1 data memory map
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 54 m aster t ransmitter and m aster r eceiver m odes the master mode is entered in the main program. to enter the master transmitter mode, the main program must first load the internal data ram with the slave address, data bytes, and the number of data bytes to be transmitted. to enter the master receiver mode, the main program must first load the internal data ram with the slave address and the number of data bytes to be received. the r/w bit determines whether sio1 operates in the master transmitter or master receiver mode. master mode operation commences when the sta bit in s1cion is set by the setb instruction and data transfer is controlled by the master state service routines in accordance with table 9, table 10, figure 22, and figure 23. in the example below, 4 bytes are transferred. there is no repeated start condition. in the event of lost arbitration, the transfer is restarted when the bus becomes free. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. if a slave device returns a not acknowledge, a stop condition is generated. a repeated start condition can be included in the serial transfer if the sta flag is set instead of the sto flag in the state service routines vectored to by status codes 28h and 58h. additional software must be written to determine which data is transferred after a repeated start condition. s lave t ransmitter and s lave r eceiver m odes after initialization, sio1 continually tests the i 2 c bus and branches to one of the slave state service routines if it detects its own slave address or the general call address (see table 11, table 12, figure 24, and figure 25). if arbitration was lost while in the master mode, the master mode is restarted after the current transfer. if a bus error occurs, the i 2 c bus is released and sio1 enters the not selected slave receiver mode. in the slave receiver mode, a maximum of 8 received data bytes can be stored in the internal data ram. a maximum of 8 bytes ensures that other ram locations are not overwritten if a master sends more bytes. if more than 8 bytes are transmitted, a not acknowledge is returned, and sio1 enters the not addressed slave receiver mode. a maximum of one received data byte can be stored in the internal data ram after a general call address is detected. if more than one byte is transmitted, a not acknowledge is returned and sio1 enters the not addressed slave receiver mode. in the slave transmitter mode, data to be transmitted is obtained from the same locations in the internal data ram that were previously loaded by the main program. after a not acknowledge has been returned by a master receiver device, sio1 enters the not addressed slave mode. a dapting the s oftware for d ifferent a pplications the following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. if one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked. this example does not include any time-out routines. in the slave modes, time-out routines are not very useful since, in these modes, sio1 behaves essentially as a passive device. in the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. this time period is defined by the system connected to the i 2 c bus.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 55 !******************************************************************************************************** ! sio1 equate list !******************************************************************************************************** !******************************************************************************************************** ! locations of the sio1 special function registers !******************************************************************************************************** 00d8 s1con 0xd8 00d9 s1sta 0xd9 00da s1dat 0xda 00db s1adr 0xdb 00a8 ien0 0xa8 00b8 ip0 02b8 !******************************************************************************************************** ! bit locations !******************************************************************************************************** 00dd sta 0xdd ! sta bit in s1con 00bd sio1hp 0xbd ! ip0, sio1 priority bit !******************************************************************************************************** ! immediate data to write into register s1con !******************************************************************************************************** 00d5 ens1_notsta_sto_notsi_aa_cr0 0xd5 ! generates stop ! (cr0 = 100khz) 00c5 ens1_notsta_notsto_notsi_aa_cr0 0xc5 ! releases bus and ! ack 00c1 ens1_notsta_notsto_notsi_notaa_cr0 0xc1 ! releases bus and ! not ack 00e5 ens1_sta_notsto_notsi_aa_cr0 0xe5 ! releases bus and ! set sta !******************************************************************************************************** ! general immediate data !******************************************************************************************************** 0031 ownsla 0x31 ! own sla+general call ! must be written into s1adr 00a0 ensio1 0xa0 ! ea+es1, enable sio1 interrupt ! must be written into ien0 0001 pag1 0x01 ! select pag1 as hadd 00c0 slaw 0xc0 ! sla+w to be transmitted 00c1 slar 0xc1 ! sla+r to be transmitted 0018 selrb3 0x18 ! select register bank 3 !******************************************************************************************************** ! locations in data ram !******************************************************************************************************** 0030 mtd 0x30 ! mst/trx/data base address 0038 mrd 0x38 ! mst/rec/data base address 0040 srd 0x40 ! slv/rec/data base address 0048 std 0x48 ! slv/trx/data base address 0053 backup 0x53 ! backup from numbytmst ! to restore numbytmst in case ! of an arbitration loss. 0052 numbytmst 0x52 ! number of bytes to transmit ! or receive as mst. 0051 sla 0x51 ! contains sla+r/w to be ! transmitted. 0050 hadd 0x50 ! high address byte for state 0 ! till state 25.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 56 !******************************************************************************************************** ! initialization routine ! example to initialize iic interface as slave receiver or slave transmitter and ! start a master transmit or a master receive function. 4 bytes will be transmitted or received. !******************************************************************************************************** .sect strt .base 0x00 0000 4100 ajmp init ! reset .sect initial .base 0x200 0200 75db31 init: mov s1adr,#ownsla ! load own sla + enable ! general call recognition 0203 d296 setb p1(6) ! p1.6 high level. 0205 d297 setb p1(7) ! p1.7 high level. 0207 755001 mov hadd,#pag1 020a 43a8a0 orl ien0,#ensio1 ! enable sio1 interrupt 020d c2bd clr sio1hp ! sio1 interrupt low priority 020f 75d8c5 mov s1con, #ens1_notsta_notsto_notsi_aa_cr0 ! initialize slv funct. !******************************************************************************************************** ! ! start master transmit function ! 0212 755204 mov numbytmst,#0x4 ! transmit 4 bytes. 0215 7551c0 mov sla,#slaw ! sla+w, transmit funct. 0218 d2dd setb sta ! set sta in s1con ! ! start master receive function ! 021a 755204 mov numbytmst,#0x4 ! receive 4 bytes. 021d 7551c1 mov sla,#slar ! sla+r, receive funct. 0220 d2dd setb sta ! set sta in s1con !******************************************************************************************************** ! sio1 interrupt routine !******************************************************************************************************** .sect intvec ! sio1 interrupt vector .base 0x00 ! s1sta and hadd are pushed onto the stack. ! they serve as return address for the ret instruction. ! the ret instruction sets the program counter to address hadd, ! s1sta and jumps to the right subroutine. 002b c0d0 push psw ! save psw 002d c0d9 push s1sta 002f c050 push hadd 0031 22 ret ! jmp to address hadd,s1sta. ! ! state : 00, bus error. ! action : enter not addressed slv mode and release bus. sto reset. ! .sect st0 .base 0x100 0100 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si ! set sto,aa 0103 d0d0 pop psw 0105 32 reti
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 57 !******************************************************************************************************** !******************************************************************************************************** ! master state service routines !******************************************************************************************************** ! state 08 and state 10 are both for mst/trx and mst/rec. ! the r/w bit decides whether the next state is within ! mst/trx mode or within mst/rec mode. !******************************************************************************************************** ! ! state : 08, a, start condition has been transmitted. ! action : sla+r/w are transmitted, ack bit is received. ! .sect mts8 .base 0x108 0108 8551da mov s1dat,sla ! load sla+r/w 010b 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 ! ! state : 10, a repeated start condition has been ! transmitted. ! action : sla+r/w are transmitted, ack bit is received. ! .sect mts10 .base 0x110 0110 8551da mov s1dat,sla ! load sla+r/w 0113 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si 010e 01a0 ajmp initbase1 .sect ibase1 .base 0xa0 00a0 75d018 initbase1: mov psw,#selrb3 00a3 7930 mov r1,#mtd 00a5 7838 mov r0,#mrd 00a7 855253 mov backup,numbytmst ! save initial value 00aa d0d0 pop psw 00ac 32 reti !******************************************************************************************************** !******************************************************************************************************** ! master transmitter state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 18, previous state was state 8 or state 10, sla+w have been transmitted, ! ack has been received. ! action : first data is transmitted, ack bit is received. ! .sect mts18 .base 0x118 0118 75d018 mov psw,#selrb3 011b 87da mov s1dat,@r1 011d 01b5 ajmp con
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 58 ! ! state : 20, sla+w have been transmitted, not ack has been received ! action : transmit stop condition. ! .sect mts20 .base 0x120 0120 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0123 d0d0 pop psw 0125 32 reti ! ! state : 28, data of s1dat have been transmitted, ack received. ! action : if transmitted data is last data then transmit a stop condition, ! else transmit next data. ! .sect mts28 .base 0x128 0128 d55285 djnz numbytmst,notldat1 ! jmp if not last data 012b 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! clr si, set aa 012e 01b9 ajmp retmt .sect mts28sb .base 0x0b0 00b0 75d018 notldat1: mov psw,#selrb3 00b3 87da mov s1dat,@r1 00b5 75d8c5 con: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00b8 09 inc r1 00b9 d0d0 retmt : pop psw 00bb 32 reti ! ! state : 30, data of s1dat have been transmitted, not ack received. ! action : transmit a stop condition. ! .sect mts30 .base 0x130 0130 75d8d5 mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 0133 d0d0 pop psw 0135 32 reti ! ! state : 38, arbitration lost in sla+w or data. ! action : bus is released, not addressed slv mode is entered. ! a new start condition is transmitted when the iic bus is free again. ! .sect mts38 .base 0x138 0138 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 013b 855352 mov numbytmst,backup 013e 01b9 ajmp retmt
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 59 !******************************************************************************************************** !******************************************************************************************************** ! master receiver state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 40, previous state was state 08 or state 10, ! sla+r have been transmitted, ack received. ! action : data will be received, ack returned. ! .sect mts40 .base 0x140 0140 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr sta, sto, si set aa 0143 d0d0 pop psw 32 reti ! ! state : 48, sla+r have been transmitted, not ack received. ! action : stop condition will be generated. ! .sect mts48 .base 0x148 0148 75d8d5 stop: mov s1con,#ens1_notsta_sto_notsi_aa_cr0 ! set sto, clr si 014b d0d0 pop psw 014d 32 reti ! ! state : 50, data have been received, ack returned. ! action : read data of s1dat. ! data will be received, if it is last data then not ack will be returned else ack will be returned. ! .sect mrs50 .base 0x150 0150 75d018 mov psw,#selrb3 0153 a6da mov @r0,s1dat ! read received data 0155 01c0 ajmp rec1 .sect mrs50s .base 0xc0 00c0 d55205 rec1: djnz numbytmst,notldat2 00c3 75d8c1 mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00c6 8003 sjmp retmr 00c8 75d8c5 notldat2: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00cb 08 retmr: inc r0 00cc d0d0 pop psw 00ce 32 reti ! ! state : 58, data have been received, not ack returned. ! action : read data of s1dat and generate a stop condition. ! .sect mrs58 .base 0x158 0158 75d018 mov psw,#selrb3 015b a6da mov @r0,s1dat 015d 80e9 sjmp stop
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 60 !******************************************************************************************************** !******************************************************************************************************** ! slave receiver state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : 60, own sla+w have been received, ack returned. ! action : data will be received and ack returned. ! .sect srs60 .base 0x160 0160 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0163 75d018 mov psw,#selrb3 0166 01d0 ajmp initsrd .sect insrd .base 0xd0 00d0 7840 initsrd: mov r0,#srd 00d2 7908 mov r1,#8 00d4 d0d0 pop psw 00d6 32 reti ! ! state : 68, arbitration lost in sla and r/w as mst ! own sla+w have been received, ack returned ! action : data will be received and ack returned. ! sta is set to restart mst mode after the bus is free again. ! .sect srs68 .base 0x168 0168 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 016b 75d018 mov psw,#selrb3 016e 01d0 ajmp initsrd ! ! state : 70, general call has been received, ack returned. ! action : data will be received and ack returned. ! .sect srs70 .base 0x170 0170 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 0173 75d018 mov psw,#selrb3 ! initialize srd counter 0176 01d0 ajmp initsrd ! ! state : 78, arbitration lost in sla+r/w as mst. ! general call has been received, ack returned. ! action : data will be received and ack returned. ! sta is set to restart mst mode after the bus is free again. ! .sect srs78 .base 0x178 0178 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 017b 75d018 mov psw,#selrb3 ! initialize srd counter 017e 01d0 ajmp initsrd
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 61 ! ! state : 80, previously addressed with own sla. data received, ack returned. ! action : read data. ! if received data was the last ! then superfluous data will be received and not ack returned else next data will be received and ack returned. ! .sect srs80 .base 0x180 0180 75d018 mov psw,#selrb3 0183 a6da mov @r0,s1dat ! read received data 0185 01d8 ajmp rec2 .sect srs80s .base 0xd8 00d8 d906 rec2: djnz r1,notldat3 00da 75d8c1 ldat: mov s1con,#ens1_notsta_notsto_notsi_notaa_cr0 ! clr si,aa 00dd d0d0 pop psw 00df 32 reti 00e0 75d8c5 notldat3: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00e3 08 inc r0 00e4 d0d0 retsr: pop psw 00e6 32 reti ! ! state : 88, previously addressed with own sla. data received not ack returned. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01. ! .sect srs88 .base 0x188 0188 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 018b 01e4 ajmp retsr ! ! state : 90, previously addressed with general call. ! data has been received, ack has been returned. ! action : read data. after general call only one byte will be received with ack ! the second data will be received with not ack. ! data will be received and not ack returned. ! .sect srs90 .base 0x190 0190 75d018 mov psw,#selrb3 0193 a6da mov @r0,s1dat ! read received data 0195 01da ajmp ldat ! ! state : 98, previously addressed with general call. ! data has been received, not ack has been returned. ! action : no save of data, enter not addressed slv mode. recognition of own sla. general call recognized, if s1adr. 01. ! .sect srs98 .base 0x198 0198 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 019b d0d0 pop psw 019d 32 reti
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 62 ! ! state : a0, a stop condition or repeated start has been received, ! while still addressed as slv/rec or slv/trx. ! action : no save of data, enter not addressed slv mode. ! recognition of own sla. general call recognized, if s1adr. 01. ! .sect srsa0 .base 0x1a0 01a0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01a3 d0d0 pop psw 01a5 32 reti !******************************************************************************************************** !******************************************************************************************************** ! slave transmitter state service routines !******************************************************************************************************** !******************************************************************************************************** ! ! state : a8, own sla+r received, ack returned. ! action : data will be transmitted, a bit received. ! .sect stsa8 .base 0x1a8 01a8 8548da mov s1dat,std ! load data in s1dat 01ab 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01ae 01e8 ajmp initbase2 .sect ibase2 .base 0xe8 00e8 75d018 initbase2: mov psw,#selrb3 00eb 7948 mov r1, #std 00ed 09 inc r1 00ee d0d0 pop psw 00f0 32 reti ! ! state : b0, arbitration lost in sla and r/w as mst. own sla+r received, ack returned. ! action : data will be transmitted, a bit received. ! sta is set to restart mst mode after the bus is free again. ! .sect stsb0 .base 0x1b0 01b0 8548da mov s1dat,std ! load data in s1dat 01b3 75d8e5 mov s1con,#ens1_sta_notsto_notsi_aa_cr0 01b6 01e8 ajmp initbase2
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 63 ! ! state : b8, data has been transmitted, ack received. ! action : data will be transmitted, ack bit is received. ! .sect stsb8 .base 0x1b8 01b8 75d018 mov psw,#selrb3 01bb 87da mov s1dat,@r1 01bd 01f8 ajmp scon .sect scn .base 0xf8 00f8 75d8c5 scon: mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 00fb 09 inc r1 00fc d0d0 pop psw 00fe 32 reti ! ! state : c0, data has been transmitted, not ack received. ! action : enter not addressed slv mode. ! .sect stsc0 .base 0x1c0 01c0 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01c3 d0d0 pop psw 01c5 32 reti ! ! state : c8, last data has been transmitted (aa=0), ack received. ! action : enter not addressed slv mode. ! .sect stsc8 .base 0x1c8 01c8 75d8c5 mov s1con,#ens1_notsta_notsto_notsi_aa_cr0 ! clr si, set aa 01cb d0d0 pop psw 01cd 32 reti !******************************************************************************************************** !******************************************************************************************************** ! end of sio1 interrupt routine !******************************************************************************************************** !******************************************************************************************************** figure 30. internal and external data memory address space with extram = 0
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 64 interrupt priority structure the p8xc660x2/661x2 has an 8/9 source four-level interrupt structure (see table 15). there are 4 sfrs associated with the four-level interrupt. they are the ie, ien1, ip, and iph. (see figures 31, 32, and 33.) the iph (interrupt priority high) register makes the four-level interrupt structure possible. the iph is located at sfr address b7h. the function of the iph sfr, when combined with the ip sfr, determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: table 14. priority bits interrupt priority level iph.x ip.x interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) table 15. interrupt table p8xc661x2 source polling priority request bits hardware clear? vector address x0 1 ie0 n (l) 1 y (t) 2 03h sio1 (i2c) 2 n 2bh sio2 (i2c) 3 n 43h t0 4 tp0 y 0bh x1 5 ie1 n (l) y (t) 13h t1 6 tf1 y 1bh sp 7 ri, ti n 23h t2 8 tf2, exf2 n 3bh pca 9 cf, ccfn n = 04 n 33h notes: 1. l = level activated 2. t = transition activated table 16. interrupt table p8xc662x2 source polling priority request bits hardware clear? vector address x0 1 ie0 n (l) 1 y (t) 2 03h sio1 (i2c) 2 n 2bh t0 3 tp0 y 0bh x1 4 ie1 n (l) y (t) 13h t1 5 tf1 y 1bh sp 6 ri, ti n 23h t2 7 tf2, exf2 n 3bh pca 8 cf, ccfn n = 04 n 33h notes: 1. l = level activated 2. t = transition activated the priority scheme for servicing the interrupts is the same as that for the 80c51, except there are four interrupt levels rather than two as on the 80c51. an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 65 ex0 ie (0a8h) enable bit = 1 enables the interrupt. enable bit = 0 disables it. bit symbol function ie.7 ea global disable bit. if ea = 0, all interrupts are disabled. if ea = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. ie.6 ec pca interrupt enable bit ie.5 et2 timer 2 interrupt enable bit. ie.4 es serial port interrupt enable bit. ie.3 et1 timer 1 interrupt enable bit. ie.2 ex1 external interrupt 1 enable bit. ie.1 et0 timer 0 interrupt enable bit. ie.0 ex0 external interrupt 0 enable bit. su01290 et0 ex1 et1 es et2 ec ea 0 1 2 3 4 5 6 7 figure 31. ie registers px0 ip (0b8h) priority bit = 1 assigns high priority priority bit = 0 assigns low priority bit symbol function ip.7 ip.6 ppc pca interrupt priority bit ip.5 pt2 timer 2 interrupt priority bit. ip.4 ps serial port interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.2 px1 external interrupt 1 priority bit. ip.1 pt0 timer 0 interrupt priority bit. ip.0 px0 external interrupt 0 priority bit. su01291 pt0 px1 pt1 ps pt2 ppc 0 1 2 3 4 5 6 7 figure 32. ip registers px0h iph (b7h) priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function iph.7 iph.6 ppch pca interrupt priority bit iph.5 pt2h timer 2 interrupt priority bit high. iph.4 psh serial port interrupt priority bit high. iph.3 pt1h timer 1 interrupt priority bit high. iph.2 px1h external interrupt 1 priority bit high. iph.1 pt0h timer 0 interrupt priority bit high. iph.0 px0h external interrupt 0 priority bit high. su01292 pt0h px1h pt1h psh pt2h ppch 0 1 2 3 4 5 6 7 figure 33. iph registers
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 66 reduced emi mode the ao bit (auxr.0) in the auxr register when set disables the ale output unless the cpu needs to perform an off-chip memory access. reduced emi mode auxr (8eh) 765432 1 0 srd fast/ std i 2 c extram ao auxr.0 ao see more detailed description in figure 48. dual dptr the dual dptr structure (see figure 34) is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 that allows the program code to switch between them. ? new register name: auxr1# ? sfr address: a2h ? reset value: xxxxxxx0b auxr1 (a2h) 76 5 43210 lpep gps 0 dps where: dps = auxr1/bit0 = switches between dptr0 and dptr1. select reg dps dptr0 0 dptr1 1 the dps bit status should be saved by software when switching between dptr0 and dptr1. the gf2 bit is a general purpose user-defined flag. note that bit 2 is not writable and is always read as a zero. this allows the dps bit to be quickly toggled simply by executing an inc auxr1 instruction without affecting the gf2 bit. dps dptr1 dptr0 dph (83h) dpl (82h) external data memory su00745a bit0 auxr1 figure 34. dptr instructions the instructions that refer to dptr refer to the data pointer that is currently selected using the auxr1/bit 0 register. the six instructions that use the dptr are as follows: inc dptr increments the data pointer by 1 mov dptr, #data16 loads the dptr with a 16-bit constant mov a, @ a+dptr move code byte relative to dptr to acc movx a, @ dptr move external ram (16-bit address) to acc movx @ dptr , a move acc to external ram (16-bit address) jmp @ a + dptr jump indirect relative to dptr the data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the sfrs. see application note an458 for more details.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 67 programmable counter array (pca) the programmable counter array available on the p8xc66xx2 is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p1.3 (cex0), module 1 to p1.4 (cex1), etc. the basic pca configuration is shown in figure 35. the pca timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p1.2). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 38): cps1 cps0 pca timer count source 0 0 1/6 oscillator frequency (6-clock mode); 1/12 oscillator frequency (12-clock mode) 0 1 1/2 oscillator frequency (6-clock mode); 1/4 oscillator frequency (12-clock mode) 1 0 timer 0 overflow 1 1 external input at eci pin in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 36. the watchdog timer function is implemented in module 4 (see figure 45). the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to figure 39). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the pca interrupt system shown in figure 37. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 40). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. figure 41 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p1.3/cex0 p1.4/cex1 p1.5/cex2 p1.6/cex3 p1.7/cex4 16 bits pca timer/counter time base for pca modules 16 bits su00032 figure 35. programmable counter array (pca)
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 68 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (c1h) cidl wdte cps1 cps0 ecf osc/6 (6 clock mode) or osc/12 (12 clock mode) timer 0 overflow external input (p1.2/eci) decode 00 01 10 11 su01256 osc/2 (6 clock mode) or osc/4 (12 clock mode) figure 36. pca timer/counter module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf ccapmn.0 eccfn to interrupt priority decoder ccon (c0h) ie.6 ec ie.7 ea su01097 figure 37. pca interrupt system
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 69 cmod address = d9h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc /6 in 6-clock mode (f osc /12 in 12-clock mode) 0 1 1 internal clock, f osc /2 in 6-clock mode (f osc /4 in 12-clock mode) 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p1.2 pin (max. rate = f osc /4 in 6-clock mode, f ocs /8 in 12-clock mode) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su01318 76543210 figure 38. cmod: pca counter mode register ccon address = d8h reset value = 00x0 0000b cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01319 76543210 figure 39. ccon: pca counter control register
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 70 ccapmn address ccapm0 0dah ccapm1 0dbh ccapm2 0dch ccapm3 0ddh ccapm4 0deh reset value = x000 0000b ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01320 76543210 figure 40. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 41. pca module modes (ccapmn register) pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. refer to figure 42. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 43). high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 44). pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 45 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 71 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su01608 figure 42. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su01609 figure 43. pca compare mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 72 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su01610 figure 44. pca high speed output mode cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su01611 figure 45. pca pwm mode
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 73 ecomn cappn capnn matn togn pwmn eccfn ccapm4 (deh) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4l reset write to ccap4h 10 1 cmod (d9h) cidl wdte cps1 cps0 ecf x su01612 module 4 figure 46. pca watchdog timer mode (module 4 only) pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 46 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. figure 47 shows the code for initializing the watchdog timer. module 4 can be configured in either compare mode, and the wdte bit in cmod must also be set. the user's software then must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine in figure 47. this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 74 init_watchdog: mov ccapm4, #4ch ; module 4 in compare mode mov ccap4l, #0ffh ; write to low byte first mov ccap4h, #0ffh ; before pca timer counts up to ; ffff hex, these compare values ; must be changed orl cmod, #40h ; set the wdte bit to enable the ; watchdog timer without changing ; the other bits in cmod ; ;******************************************************************** ; ; main program goes here, but call watchdog periodically. ; ;******************************************************************** ; watchdog: clr ea ; hold off interrupts mov ccap4l, #00 ; next compare value is within mov ccap4h, ch ; 255 counts of the current pca setb ea ; timer value ret figure 47. pca watchdog timer initialization code
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 75 expanded data ram addressing the p8xc660x2/661x2 has internal data memory that is mapped into four separate segments: the lower 128 bytes of ram, upper 128 bytes of ram, 128 bytes special function register (sfr), and 256 bytes expanded ram (eram) (768 bytes for the rd2). the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the 256/768-bytes expanded ram (eram, 00h 1ffh/2ffh) are indirectly accessed by move external instruction, movx, and with the extram bit cleared, see figure 48. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h,#data accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0,acc where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the eram can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory is physically located on-chip, logically occupies the first 256/768 bytes of external data memory in the p8xc660x2/661x2. with extram = 0, the eram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to eram will not affect ports p0, p3.6 (wr#) and p3.7 (rd#). p2 sfr is output during external addressing. for example, with extram = 0, movx @r0,acc where r0 contains 0a0h, accesses the eram at address 0a0h rather than external memory. an access to external data memory locations higher than the eram will be performed with the movx dptr instructions in the same way as in the standard 80c51, so with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. refer to figure 49. with extram = 1, movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an 8-bit address multiplexed with data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a 16-bit address. port 2 outputs the high-order eight address bits (the contents of dph) while port 0 multiplexes the low-order eight address bits (dpl) with data. movx @ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the eram.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 76 auxr reset value = xx0x 0x00b e e srd e fme e extram ao not bit addressable bit: symbol function ao disable/enable ale ao operating mode 0 ale is emitted at a constant rate of 1 / 6 the oscillator frequency (12-clock mode; 1 / 3 f osc in 6-clock mode). 1 ale is active only during off-chip memory access. extram internal/external ram access using movx @ri/@dptr extram operating mode 0 internal eram access using movx @ri/@dptr. 1 external data memory access. fme fast mode enable, switches between the standard and the fast data-transfer mode for the sio1 i 2 c serial port (a one-time set bit, cleared by chip-reset only) fme operating mode 0 100 kbit/s standard mode selected. 1 400 kbit/s fast mode selected. srd slew-rate control-circuit disable, switches between the minimum and the maximum slew-rate of the scl1 and sda1 pins of the sio2 i 2 c serial port. srd operating mode 0 minimum output slew-rate. 1 maximum output slew-rate. e not implemented, reserved for future use*. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01749 76543210 address = 8eh figure 48. auxr: auxiliary register eram 256 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function register 100 ff 00 ff 00 80 80 external data memory 3fff 0000 su01750 figure 49. internal and external data memory address space with extram = 0
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 77 hardware watchdog timer (one-time enabled with reset-out for p8xc66xx2) the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is disabled at reset. to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when the wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when the wdt overflows, it will drive an output reset high pulse at the rst-pin (see the note below). using the wdt to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when the wdt is enabled, the user needs to service it by writing 01eh and 0e1h to wdtrst to avoid a wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset the device. when the wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycles. to reset the wdt, the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when the wdt overflows, it will generate an output reset pulse at the reset pin (see note below). the reset pulse duration is 98 t osc (6-clock mode; 196 in 12-clock mode), where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 78 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 or 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 4 0.5 to +6.0 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 4. transient voltage only. ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c clock frequency range symbol figure parameter operating mode power supply voltage min max unit 1/t clcl 55 oscillator frequency 6-clock 5 v 10% 0 30 mhz 6-clock 2.7 v to 5.5 v 0 16 mhz 12-clock 5 v 10% 0 33 mhz 12-clock 2.7 v to 5.5 v 0 16 mhz
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 79 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c; v cc = 2.7 v to 5.5 v ; v ss = 0 v (16 mhz max. cpu clock) symbol parameter test conditions limits unit min typ 1 max v il input low voltage 11 (except ea , scl, sda) 4.0 v < v cc < 5.5 v 0.5 0.2 v cc 0.1 v 2.7 v < v cc < 4.0 v 0.5 0.7 v cc v v il1 low level input voltage ea 0.5 0.2 v dd 0.35 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 11 0.7 v cc v cc +0.5 v v ih2 input high voltage, sdl and sda 13 0.7 v dd 5.5 v v ol output low voltage, ports 1, 2 8 v cc = 2.7 v; i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 7,8 v cc = 2.7 v; i ol = 3.2 ma 2 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 2.7 v; i oh = 20 a v cc 0.7 v v cc = 4.5 v; i oh = 30 a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 2.7 v; i oh = 3.2 ma v cc 0.7 v v hys hysteresis of schmitt trigger inputs scl and sda (fast mode) 0.5v dd 14 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 50 a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v; see note 4 650 a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 a i li2 input leakage current scl and sda 0 v < v in < 5.5 v 0 v < v dd < 5.5 v 10 a i cc power supply current (see figure 58 and source code): active mode @ 16 mhz a idle mode @ 16 mhz a power-down mode or clock stopped (see figure 54 for conditions) 12 t amb = 0 c to 70 c 2 30 a t amb = 40 c to +85 c 3 50 a v ram ram keep-alive voltage 1.2 v r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. values listed are based on tests conducted on limited number of samples at room temperatu re. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be des irable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 60 through 63 for i cc test conditions and figure 58 for i cc vs. frequency 12-clock mode characteristics: active mode (operating): i cc = 1.0 ma + 1.1 ma freq.[mhz] active mode (reset): i cc = 7.0 ma + 1.1 ma freq.[mhz] idle mode: i cc = 1.0 ma + 0.44 ma freq.[mhz] 6. this value applies to t amb = 0 c to +70 c. for t amb = 40 c to +85 c, i tl = 750 a. 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 80 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf). 11. to improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the rst pin, and a nominal 15 ns gl itch rejection circuitry has been added to the int0 and int1 pins. previous devices provided only an inherent 5 ns of glitch rejection. 12. power down mode for 3 v range: commercial temperature range typ: 0.5 a, max. 20 a; industrial temperature range typ. 1.0 a, max. 30 a; 13. the input threshold voltage of scl and sda (sio1) meets the i 2 c specification, so an input voltage below 0.3 v dd will be recognized as a logic 0 while an input voltage above 0.7 v dd will be recognized as a logic 1. 14. not 100% tested.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 81 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c; v cc = 5 v 10% ; v ss = 0 v (30/33 mhz max. cpu clock) symbol parameter test conditions limits unit min typ 1 max v il input low voltage 11 (except ea , scl, sda) 4.5 v < v cc < 5.5 v 0.5 0.2 v cc 0.1 v v il1 low level input voltage ea 0.5 0.2 v dd 0.35 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 11 0.7 v cc v cc +0.5 v v ih2 input high voltage, sdl and sda 12 0.7 v dd 5.5 v v ol output low voltage, ports 1, 2, 3 8 v cc = 4.5 v; i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 7, 8 v cc = 4.5 v; i ol = 3.2 ma 2 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 4.5 v; i oh = 30 a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 4.5 v; i oh = 3.2 ma v cc 0.7 v v hys hysteresis of schmitt trigger inputs scl and sda (fast mode) 13 0.5v dd v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 50 a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v; see note 4 650 a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 a i li2 input leakage current scl and sda 0 v < v in < 5.5 v 0 v < v dd < 5.5 v 10 a i cc power supply current active mode (see note 5) idle mode (see note 5) power-down mode or clock stopped (see figure 63 for conditions) t amb = 0 c to 70 c 2 30 a t amb = 40 c to +85 c 3 50 a v ram ram keep-alive voltage 1.2 v r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5 v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 60 through 63 for i cc test conditions and figure 58 for i cc vs. frequency. 12-clock mode characteristics: active mode (operating): i cc = 1.0 ma + 1.1 ma freq.[mhz] active mode (reset): i cc = 7.0 ma + 1.1 ma freq.[mhz] idle mode: i cc = 1.0 ma + 0.44 ma freq.[mhz] 6. this value applies to t amb = 0 c to +70 c. for t amb = 40 c to +85 c, i tl = 750 ma . 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf). 11. to improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the rst pin, and a nominal 15 ns gl itch rejection circuitry has been added to the int0 and int1 pins. previous devices provided only an inherent 5 ns of glitch rejection.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 82 12. the input threshold voltage of scl and sda (sio1) meets the i 2 c specification, so an input voltage below 0.3 v dd will be recognized as a logic 0 while an input voltage above 0.7 v dd will be recognized as a logic 1. 13. not 100% tested.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 83 ac electrical characteristics (12-clock mode, 5 v 10% operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 5 v 10%, v ss = 0 v 1,2,3,4 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 55 oscillator frequency 0 33 mhz t lhll 50 ale pulse width 2 t clcl 8 117 ns t avll 50 address valid to ale low t clcl 13 49.5 ns t llax 50 address hold after ale low t clcl 20 42.5 ns t lliv 50 ale low to valid instruction in 4 t clcl 35 215 ns t llpl 50 ale low to psen low t clcl 10 52.5 ns t plph 50 psen pulse width 3 t clcl 10 177.5 ns t pliv 50 psen low to valid instruction in 3 t clcl 35 152.5 ns t pxix 50 input instruction hold after psen 0 0 ns t pxiz 50 input instruction float after psen t clcl 10 52.5 ns t aviv 50 address to valid instruction in 5 t clcl 35 277.5 ns t plaz 50 psen low to address float 10 10 ns data memory t rlrh 51 rd pulse width 6 t clcl 20 355 ns t wlwh 52 wr pulse width 6 t clcl 20 355 ns t rldv 51 rd low to valid data in 5 t clcl 35 277.5 ns t rhdx 51 data hold after rd 0 0 ns t rhdz 51 data float after rd 2 t clcl 10 115 ns t lldv 51 ale low to valid data in 8 t clcl 35 465 ns t avdv 51 address to valid data in 9 t clcl 35 527.5 ns t llwl 51, 52 ale low to rd or wr low 3 t clcl 15 3 t clcl +15 172.5 202.5 ns t avwl 51, 52 address valid to wr low or rd low 4 t clcl 15 235 ns t qvwx 52 data valid to wr transition t clcl 25 37.5 ns t whqx 52 data hold after wr t clcl 15 47.5 ns t qvwh 52 data valid to wr high 7 t clcl 5 432.5 ns t rlaz 51 rd low to address float 0 0 ns t whlh 51, 52 rd or wr high to ale high t clcl 10 t clcl +10 52.5 72.5 ns external clock t chcx 55 high time 0.32 t clcl t clcl t clcx ns t clcx 55 low time 0.32 t clcl t clcl t chcx ns t clch 55 rise time 5 ns t chcl 55 fall time 5 ns shift register t xlxl 54 serial port clock cycle time 12 t clcl 750 ns t qvxh 54 output data setup to clock rising edge 10 t clcl 25 600 ns t xhqx 54 output data hold after clock rising edge 2 t clcl 15 110 ns t xhdx 54 input data hold after clock rising edge 0 0 ns t xhdv 54 clock rising edge to input data valid 5 10 t clcl 133 492 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45 ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. below 16 mhz this parameter is 8 t clcl 133.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 84 ac electrical characteristics (12-clock mode, 2.7 v to 5.5 v operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 2.7 v to 5.5 v, v ss = 0 v 1,2,3,4 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 55 oscillator frequency 0 16 mhz t lhll 50 ale pulse width 2t clcl 10 115 ns t avll 50 address valid to ale low t clcl 15 47.5 ns t llax 50 address hold after ale low t clcl 25 37.5 ns t lliv 50 ale low to valid instruction in 4 t clcl 55 195 ns t llpl 50 ale low to psen low t clcl 15 47.5 ns t plph 50 psen pulse width 3 t clcl 15 172.5 ns t pliv 50 psen low to valid instruction in 3 t clcl 55 132.5 ns t pxix 50 input instruction hold after psen 0 0 ns t pxiz 50 input instruction float after psen t clcl 10 52.5 ns t aviv 50 address to valid instruction in 5 t clcl 50 262.5 ns t plaz 50 psen low to address float 10 10 ns data memory t rlrh 51 rd pulse width 6 t clcl 25 350 ns t wlwh 52 wr pulse width 6 t clcl 25 350 ns t rldv 51 rd low to valid data in 5 t clcl 50 262.5 ns t rhdx 51 data hold after rd 0 0 ns t rhdz 51 data float after rd 2 t clcl 20 105 ns t lldv 51 ale low to valid data in 8 t clcl 55 445 ns t avdv 51 address to valid data in 9 t clcl 50 512.5 ns t llwl 51, 52 ale low to rd or wr low 3 t clcl 20 3 t clcl +20 167.5 207.5 ns t avwl 51, 52 address valid to wr low or rd low 4 t clcl 20 230 ns t qvwx 52 data valid to wr transition t clcl 30 32.5 ns t whqx 52 data hold after wr t clcl 20 42.5 ns t qvwh 52 data valid to wr high 7 t clcl 10 427.5 ns t rlaz 51 rd low to address float 0 0 ns t whlh 51, 52 rd or wr high to ale high t clcl 15 t clcl +15 47.5 77.5 ns external clock t chcx 55 high time 0.32 t clcl t clcl t clcx ns t clcx 55 low time 0.32 t clcl t clcl t chcx ns t clch 55 rise time 5 ns t chcl 55 fall time 5 ns shift register t xlxl 54 serial port clock cycle time 12 t clcl 750 ns t qvxh 54 output data setup to clock rising edge 10 t clcl 25 600 ns t xhqx 54 output data hold after clock rising edge 2 t clcl 15 110 ns t xhdx 54 input data hold after clock rising edge 0 0 ns t xhdv 54 clock rising edge to input data valid 5 10 t clcl 133 492 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45 ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. below 16 mhz this parameter is 8 t clcl 133.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 85 ac electrical characteristics (6-clock mode, 5 v 10% operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 5 v 10%, v ss = 0 v 1,2,3,4,5 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 55 oscillator frequency 0 30 mhz t lhll 50 ale pulse width t clcl 8 54.5 ns t avll 50 address valid to ale low 0.5 t clcl 13 18.25 ns t llax 50 address hold after ale low 0.5 t clcl 20 11.25 ns t lliv 50 ale low to valid instruction in 2 t clcl 35 90 ns t llpl 50 ale low to psen low 0.5 t clcl 10 21.25 ns t plph 50 psen pulse width 1.5 t clcl 10 83.75 ns t pliv 50 psen low to valid instruction in 1.5 t clcl 35 58.75 ns t pxix 50 input instruction hold after psen 0 0 ns t pxiz 50 input instruction float after psen 0.5 t clcl 10 21.25 ns t aviv 50 address to valid instruction in 2.5 t clcl 35 121.25 ns t plaz 50 psen low to address float 10 10 ns data memory t rlrh 51 rd pulse width 3 t clcl 20 167.5 ns t wlwh 52 wr pulse width 3 t clcl 20 167.5 ns t rldv 51 rd low to valid data in 2.5 t clcl 35 121.25 ns t rhdx 51 data hold after rd 0 0 ns t rhdz 51 data float after rd t clcl 10 52.5 ns t lldv 51 ale low to valid data in 4 t clcl 35 215 ns t avdv 51 address to valid data in 4.5 t clcl 35 246.25 ns t llwl 51, 52 ale low to rd or wr low 1.5 t clcl 15 1.5 t clcl +15 78.75 108.75 ns t avwl 51, 52 address valid to wr low or rd low 2 t clcl 15 110 ns t qvwx 52 data valid to wr transition 0.5 t clcl 25 6.25 ns t whqx 52 data hold after wr 0.5 t clcl 15 16.25 ns t qvwh 52 data valid to wr high 3.5 t clcl 5 213.75 ns t rlaz 51 rd low to address float 0 0 ns t whlh 51, 52 rd or wr high to ale high 0.5 t clcl 10 0.5 t clcl +10 21.25 41.25 ns external clock t chcx 55 high time 0.4 t clcl t clcl t clcx ns t clcx 55 low time 0.4 t clcl t clcl t chcx ns t clch 55 rise time 5 ns t chcl 55 fall time 5 ns shift register t xlxl 54 serial port clock cycle time 6 t clcl 375 ns t qvxh 54 output data setup to clock rising edge 5 t clcl 25 287.5 ns t xhqx 54 output data hold after clock rising edge t clcl 15 47.5 ns t xhdx 54 input data hold after clock rising edge 0 0 ns t xhdv 54 clock rising edge to input data valid 6 5 t clcl 133 179.5 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen =100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45ns is permitted. this limited bus contention will not caus e damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. data shown in the table are the best mathematical models for the set of measured values obtained in tests. if a particular pa rameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. below 16 mhz this parameter is 4 t clcl 133
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 86 ac electrical characteristics (6-clock mode, 2.7 v to 5.5 v operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc =2.7 v to 5.5 v, v ss = 0 v 1,2,3,4,5 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 55 oscillator frequency 0 16 mhz t lhll 50 ale pulse width t clcl 10 52.5 ns t avll 50 address valid to ale low 0.5 t clcl 15 16.25 ns t llax 50 address hold after ale low 0.5 t clcl 25 6.25 ns t lliv 50 ale low to valid instruction in 2 t clcl 55 70 ns t llpl 50 ale low to psen low 0.5 t clcl 15 16.25 ns t plph 50 psen pulse width 1.5 t clcl 15 78.75 ns t pliv 50 psen low to valid instruction in 1.5 t clcl 55 38.75 ns t pxix 50 input instruction hold after psen 0 0 ns t pxiz 50 input instruction float after psen 0.5 t clcl 10 21.25 ns t aviv 50 address to valid instruction in 2.5 t clcl 50 101.25 ns t plaz 50 psen low to address float 10 10 ns data memory t rlrh 51 rd pulse width 3 t clcl 25 162.5 ns t wlwh 52 wr pulse width 3 t clcl 25 162.5 ns t rldv 51 rd low to valid data in 2.5 t clcl 50 106.25 ns t rhdx 51 data hold after rd 0 0 ns t rhdz 51 data float after rd t clcl 20 42.5 ns t lldv 51 ale low to valid data in 4 t clcl 55 195 ns t avdv 51 address to valid data in 4.5 t clcl 50 231.25 ns t llwl 51, 52 ale low to rd or wr low 1.5 t clcl 20 1.5 t clcl +20 73.75 113.75 ns t avwl 51, 52 address valid to wr low or rd low 2 t clcl 20 105 ns t qvwx 52 data valid to wr transition 0.5 t clcl 30 1.25 ns t whqx 52 data hold after wr 0.5 t clcl 20 11.25 ns t qvwh 52 data valid to wr high 3.5 t clcl 10 208.75 ns t rlaz 51 rd low to address float 0 0 ns t whlh 51, 52 rd or wr high to ale high 0.5 t clcl 15 0.5 t clcl +15 16.25 46.25 ns external clock t chcx 55 high time 0.4 t clcl t clcl t clcx ns t clcx 55 low time 0.4 t clcl t clcl t chcx ns t clch 55 rise time 5 ns t chcl 55 fall time 5 ns shift register t xlxl 54 serial port clock cycle time 6 t clcl 375 ns t qvxh 54 output data setup to clock rising edge 5 t clcl 25 287.5 ns t xhqx 54 output data hold after clock rising edge t clcl 15 47.5 ns t xhdx 54 input data hold after clock rising edge 0 0 ns t xhdv 54 clock rising edge to input data valid 6 5 t clcl 133 179.5 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen =100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45ns is permitted. this limited bus contention will not caus e damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. data shown in the table are the best mathematical models for the set of measured values obtained in tests. if a particular pa rameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. below 16 mhz this parameter is 4 t clcl 133
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 87 i 2 c-bus interface timing (5 v, 3.5 mhz to 16 mhz) not tested, guaranteed by design all values referred to v ih(min) and v il(max) levels; see figure tbd symbol figure parameter i 2 c-bus unit standard mode fast mode min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 1.3 m s t hd; sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 0.6 m s t low low period of the scl clock 4.7 1.3 m s t high high period of the scl clock 4.0 0.6 m s t su; sta set-up time for a repeated start condition 4.7 0.6 m s t hd;dat data hold time: for cbus compatible masters (notes 1, 3) for i 2 cbus devices (notes 1, 2) 5.0 0 0 0.9 m s t su;dat data set-up time 250 100 3 ns t fd , t fc rise time of both sda and scl signals 1000 20 + 0.1 c b 4 300 ns t fd , t fc fall time of both sda and scl signals 300 t su; sto set-up time for stop condition 4.0 0.6 m s c b capacitive load for each bus line 400 400 pf t sp pulse width of spikes which must be suppressed by the input filter 0 50 ns notes: 1. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. 2. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low) of the scl signal. 3. a fast mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su, dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 88 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl =time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 50. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 51. external data memory read cycle
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 89 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 52. external data memory write cycle su01759 0.3 vdd sda (input/output) scl (input/output) 0.7 vdd start or repeated start condition repeated start condition stop condition start condition 0.7 v dd 0.3 v dd t su;dat3 t su;dat2 t su; sto t hd;sta t low t high t su;dat1 t hd;dat t buf t su;sta t rd t rc t fc t fd figure 53. timing sio1 (i 2 c) interface
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 90 012345678 instruction ale clock output data write to sbuf input data clear ri set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 valid valid valid valid valid valid valid valid figure 54. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 55. external clock drive v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 56. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 57. float waveform
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 91 su01684 typ active mode max idle mode i cc max = 0.22 freq. + 1.0 typ idle mode 5 481216 freq at xtal1 (mhz) 20 24 28 32 36 15 25 i cc (ma) 10 20 max active mode i cc max = 1.1 freq. + 1.0 35 30 40 figure 58. i cc vs. freq for 12-clock operation valid only within frequency specifications of the specified operating voltage /* ## as31 version v2.10 / *js* / ## ## ## source file: idd_ljmp1.asm ## list file: idd_ljmp1.lst created fri apr 20 15:51:40 2001 ## ########################################################## #0000 # auxr equ 08eh #0000 # ckcon equ 08fh # # #0000 # org 0 # # ljmp_label: 0000 /75;/8e;/01; # mov auxr,#001h ; turn off ale 0003 /02;/ff;/fd; # ljmp ljmp_label ; jump to end of address space 0005 /00; # nop # #fffd # org 0fffdh # # ljmp_label: # fffd /02;/fd;ff; # ljmp ljmp_label # ; nop # # */o su01499 figure 59. source code used in measuring i dd operational
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 92 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal su00719 figure 60. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00720 figure 61. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 62. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00016 figure 63. i cc test condition, power down mode all other pins are disconnected. v cc = 2 v to 5.5 v
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 93 eprom characteristics all these devices can be programmed by using a modified improved quick-pulse programming ? algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the family contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as being manufactured by philips. table 17 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 64 and 65. figure 66 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 64. note that the device is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 64. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 2 and 3 specified in table 17 are held at the `program code data' levels indicated in table 17. the ale/prog is pulsed low 5 times as shown in figure 65. to program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 5 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bits can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 1 and 2 as shown in figure 66. the other pins are held at the `verify code data' levels indicated in table 17. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low. the values are: (030h) = 15h indicates manufactured by philips (031h) = c9h indicates p8xc66xx2 (060h) = 01h (660) 02h (661) program/verify algorithms any algorithm in agreement with the conditions listed in table 17, and which satisfies the timing specifications, is suitable. security bits with none of the security bits programmed the code in the program memory can be verified. if the encryption table is programmed, the code will be encrypted when verified. when only security bit 1 (see table 18) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory, ea is latched on reset and all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. encryption array 64 bytes of encryption array are initially unprogrammed (all 1s). ? trademark phrase of intel corporation.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 94 table 17. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p3.7 p3.6 p3.3 read signature 1 0 1 1 0 0 0 0 x program code data 1 0 0* v pp 1 0 1 1 x verify code data 1 0 1 1 0 0 1 1 x pgm encryption table 1 0 0* v pp 1 0 1 0 x pgm security bit 1 1 0 0* v pp 1 1 1 1 x pgm security bit 2 1 0 0* v pp 1 1 0 0 x pgm security bit 3 1 0 0* v pp 0 1 0 1 x program to 6-clock mode 1 0 0* v pp 0 0 1 0 0 verify 6-clock 4 1 0 1 1 e 0 0 1 1 verify security bits 5 1 0 1 1 e 0 1 0 x notes: 1. `0' = valid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75 v 0.25 v. 3. v cc = 5 v 10% during programming and verification. 4. bit is output on p0.4 (1 = 12x, 0 = 6x). 5. security bit one is output on p0.7. security bit two is output on p0.6. security bit three is output on p0.3. * ale/prog receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while v pp is held at 12.75 v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. table 18. program security bits for eprom devices program lock bits 1, 2 sb1 sb2 sb3 protection description 1 u u u no program security features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, external execution is disabled. internal data ram is not accessible. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 95 a0a7 1 1 1 46mhz +5v pgm data +12.75v 5 pulses to ground 0 1 0 a8a13 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.5 otp a14 p3.4 su01659 p3.5 a8a15 are programming addresses (not external memory addresses per device pin out) a15 (rd2 only) figure 64. programming configuration ale/prog: ale/prog: 1 0 1 0 5 pulses t glgh = 100 m s 10 m s t ghgl = 10 m s min su00875 1234 5 see exploded view below 1 figure 65. prog waveform a0a7 1 1 1 +5v pgm data 1 1 0 0 enable 0 a8a13 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.5 otp a14 p3.4 su01660 46mhz a8a15 are programming addresses (not external memory addresses per device pin out) p3.5 a15 (rd2 only) figure 66. program verification
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 96 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 67) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 1 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s note: 1. not tested. programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p1.0p1.7 p2.0p2.5 p3.4 (a0 a14) port 0 p0.0 p0.7 (d0 d7) ale/prog ea /v pp p2.7 ** su00871 t ehsh notes: * for programming configuration see figure 64. for verification conditions see figure 66. ** see table 17. figure 67. eprom programming and verification
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 97 mask rom devices security bits with none of the security bits programmed the code in the program memory can be verified. if the encryption table is programmed, the code will be encrypted when verified. when only security bit 1 (see table 19) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory, ea is latched on reset and all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. encryption array 64 bytes of encryption array are initially unprogrammed (all 1s). table 19. program security bits program lock bits 1, 2 sb1 sb2 protection description 1 u u no program security features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 98 rom code submission for 16k rom devices (83c66x) when submitting rom code for the 16k rom devices, the following must be specified: 1. 16k byte user rom data 2. 64 byte rom encryption key 3. rom security bits. address content bit(s) comment 0000h to 3fffh data 7:0 user rom data 4000h to 403fh key 7:0 rom encryption key ffh = no encryption 4040h sec 0 rom security bit 1 0 = enable security 1 = disable security 4040h sec 1 rom security bit 2 0 = enable security 1 = disable security security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. note: security bit 2 cannot be enabled unless security bit 1 is enabled. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file.
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 99 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 100 lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 101 revision history rev date description _3 20031002 product data (9397 750 12144); ecn 853-2416 30396 dated 2003 september 30 modifications: ? corrected pin description for v ss ? corrected auxr (figure 48). _2 20030619 product data (9397 750 11439); ecn 853-2416 29870 dated 2003 apr 28 _1 20030312 product data (9397 750 11126); ecn 853-2416 29538 dated 2003 feb 13
philips semiconductors product data p8xc660x2/661x2 80c51 8-bit microcontroller family 16 kb otp/rom, 512b ram, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz), two 400kb i 2 c interfaces 2003 oct 02 102 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 10-03 document order number: 9397 750 12144

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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